Rainbow Electronics MAX17047 - Manual (Page 24)

���������������������������������������������������������������� Maxim Integrated Products 24
MAX17047
ModelGauge m3 Fuel Gauge
RelaxCFG Register (2Ah)
The RelaxCFG register defines how the device detects
if the cell is in a relaxed state. See
Figure 31 . For a cell
to be considered relaxed, current flow through the cell
must be kept at a minimum while the change in the cell’s
voltage over time, dV/dt, shows little or no change. If
AverageCurrent remains below the Load threshold while
V
CELL
changes less than the dV threshold over two
consecutive periods of dt, the cell is considered relaxed.
Figure 30 shows the RelaxCFG register format:
Load6:Load0—Sets the threshold, which the
AverageCurrent register is compared against. The
AverageCurrent register must remain below this thresh-
old value for the cell to be considered unloaded. Load is
an unsigned 7-bit value where 1 LSb = 50FV. The default
value is 800FV.
dV4:dV0—Sets the threshold, which V
CELL
is compared
against. If the cell’s voltage changes by less than dV over
two consecutive periods set by dt, the cell is considered
relaxed; dV has a range of 0 to 40mV where 1 LSb =
1.25mV. The default value is 1.75mV.
dt3:dt0—Sets the time period over which change in
V
CELL
is compared against dV. If the cell’s voltage
changes by less than dV over two consecutive periods
set by dt, the cell is considered relaxed. The default
value is 6 minutes. The comparison period is calculated
as:
Relaxation Period = 2 dt O 0.1758s
Figure 30. RelaxCFG Register Format (Input)
Figure 31. Cell Relaxation Detection
MSB—ADDRESS 2Ah LSB—ADDRESS 2Ah
Load 6 Load 5 Load 4 Load 3 Load 2 Load 1 Load 0 dV4 dV3 dV2 dV1 dV0 dt3 dt2 dt1 dt0
MSb LSb MSb LSb
LOAD 0 UNITS: 50FV/R
SENSE
(5.0mAh WHEN R
SENSE
= 0.010I)
dt1 dt2 dt3 dt4 dt5 dt6
48 TO 96
MINUTES
dV2
dV3
dV4
DISCHARGING
dV5
dV6
CELL UNLOADED
(RELAXATION BEGINS)
RELAXATION LOAD THRESHOLD
0
AVERAGE
CURRENT
CELL
VOLTAGE
FIRST
READING
BELOW
dv/dt
THRESHOLD
SECOND
READING
BELOW
dV/dt
THRESHOLD
CELL IS RELAXED
RelDt BIT SET
CELL CAPACITY IS
LEARNED LONG RELAXATION
RelDt2 BIT SET