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Pin description – Rainbow Electronics W9864G2GH User Manual

Page 5

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W9864G2GH

Publication Release Date: August 16 ,2006

- 5 -

Revision A01

5. PIN

DESCRIPTION

PIN NUMBER

PIN NAME

FUNCTION

DESCRIPTION

24, 25, 26, 27, 60, 61, 62, 63,
64, 65, 66

A0

−A10

Address

Multiplexed pins for row and column address.
Row address: A0

−A10. Column address: A0−A7.

A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.

22, 23

BS0, BS1

Bank Select

Select bank to activate during row address latch
time, or bank to read/write during address latch
time.

2, 4, 5, 7, 8, 10, 11, 13, 31, 33,
34, 36, 37, 39, 40, 42, 45, 47,
48, 50, 51, 53, 54, 56, 74, 76,
77, 79, 80, 82, 83, 85

DQ0

DQ31

Data Input/
Output

Multiplexed pins for data output and input.

20

CS

Chip Select

Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.

19

RAS

Row Address
Strobe

Command input. When sampled at the rising
edge of the clock RAS , CAS and WE
define the operation to be executed.

18

CAS

Column Address
Strobe

Referred to RAS

17

WE

Write Enable

Referred to RAS

16, 28, 59, 71

DQM0

DQM3

Input/Output
Mask

The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.

68 CLK

Clock

Inputs

System clock used to sample inputs on the rising
edge of clock.

67 CKE

Clock

Enable

CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.

1, 15, 29, 43

V

CC

Power

Power for input buffers and logic circuit inside
DRAM.

44, 58, 72, 86

V

SS

Ground

Ground for input buffers and logic circuit inside
DRAM.

3, 9, 35, 41, 49, 55, 75, 81

V

CCQ

Power for I/O
Buffer

Separated power from VCC, to improve DQ
noise immunity.

6, 12, 32, 38, 46, 52, 78, 84

V

SSQ

Ground for I/O
Buffer

Separated ground from VSS, to improve DQ
noise immunity.

14, 21, 30, 57, 69, 70, 73

NC

No Connection

No connection.(The NC pin must connect to
ground or floating.)