Table 1-20, Gpio male pin header – Xilinx SP601 Hardware UG518 User Manual
Page 38
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SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
GPIO Male Pin Header
The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight
I/Os.
Figure 1-26
and
Table 1-20
describe the J13 GPIO Male Pin Header.
X-Ref Target - Figure 1-26
Figure 1-26:
GPIO Male Pin Header Topology
1
2
3
4
5
6
7
8
9
10
11
12
J13
VCC3V3
GPIO HDR4
GPIO HDR0
GPIO HDR1
GPIO HDR2
GPIO HDR3
GPIO HDR5
GPIO HDR6
GPIO HDR7
R100
R101
R102
R103
200
200
200
200
5%
5%
5%
5%
1/16W
1
/16W
1/16W
1/16W
1
2
1
2
1
2
1
2
R99
1
1
2
2
2
2
11
200
5%
1/16W
R9
8
200
5%
1/16W
R97
200
5%
1/16W
R96
200
5%
1/16W
UG518_24_070809
Table 1-20:
GPIO Header Pins
FPGA U1 Pin
Signal Name
J13 Pin
N17
GPIO_HDR0
1
M18
GPIO_HDR1
3
A3
GPIO_HDR2
5
L15
GPIO_HDR3
7
F15
GPIO_HDR4
2
B4
GPIO_HDR5
4
F13
GPIO_HDR6
6
P12
GPIO_HDR7
8