3 device configuration, 1 external bus selection register (ebsr) – Texas Instruments TMS3320C5515 User Manual
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System Configuration and Control
1.7.3 Device Configuration
The DSP includes registers for configuring pin multiplexing, the pin output slew rate, the internal pull-ups
and pull-downs, DSP_LDO voltage selection and USB_LDO enable.
1.7.3.1
External Bus Selection Register (EBSR)
The external bus selection register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3,
UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. It also determines the
mapping of the I2S or MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is
located at port address 0x1C00. Once the bit fields of this register are changed, the routing of the signals
takes place on the next CPU clock cycle.
Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15]
can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE = 1, the
EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin retains its EMIF
functionality.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register (for more information on clock gating
peripherals, see
). After the external bus selection register has been modified, you must
reset the peripherals before using them through the Peripheral Software Reset Counter Register.
After the boot process is complete, the external bus selection register must be modified only once, during
device configuration. Continuously switching the EBSR configuration is not supported.
The external bus selection register (EBSR) is shown in
and described in
.
Figure 1-35. External Bus Selection Register (EBSR) [1C00h]
15
14
12
11
10
9
8
Reserved
PPMODE
SP1MODE
SP0MODE
R-0
R/W-000
R/W-00
R/W-00
7
6
5
4
3
2
1
0
Reserved
Reserved
A20_MODE
A19_MODE
A18_MODE
A17_MODE
A16_MODE
A15_MODE
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
61
SPRUFX5A – October 2010 – Revised November 2010
System Control
Copyright © 2010, Texas Instruments Incorporated