Texas Instruments TMS3320C5515 - Manual (Page 6)

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List of Tables
1-1. ............................................................................................................................... 14
1-2. DARAM Blocks
............................................................................................................
17
1-3. SARAM Blocks
.............................................................................................................
18
1-4. SAROM Blocks ............................................................................................................ 19
1-5. PLL Output Frequency Configuration ................................................................................... 24
1-6. CLKOUT Control Source Select Register (CCSSR) Field Descriptions ............................................ 25
1-7. Clock Generator Control Register Bits Used In BYPASS MODE
...................................................
27
1-8. Output Frequency in Bypass Mode
.....................................................................................
27
1-9. Clock Generator Control Register Bits Used In PLL Mode .......................................................... 27
1-10. PLL Clock Frequency Ranges ........................................................................................... 28
1-11. Examples of Selecting a PLL MODE Frequency, When CLK_SEL=L ............................................. 29
1-12. Clock Generator Registers
...............................................................................................
29
1-13. Clock Generator Control Register 1 (CGCR1) Field Descriptions
..................................................
30
1-14. Clock Generator Control Register 2 (CGCR2) Field Descriptions .................................................. 30
1-15. Clock Generator Control Register 3 (CGCR3) Field Descriptions .................................................. 31
1-16. Clock Generator Control Register 4 (CGCR4) Field Descriptions .................................................. 31
1-17. Clock Configuration Register 1 (CCR1) Field Descriptions
..........................................................
32
1-18. Clock Configuration Register 2 (CCR2) Field Descriptions
..........................................................
32
1-19. Power Management Features ........................................................................................... 33
1-20. DSP Power Domains ...................................................................................................... 34
1-21. Idle Configuration Register (ICR) Field Descriptions ................................................................. 36
1-22. Idle Status Register (ISTR) Field Descriptions
........................................................................
37
1-23. CPU Clock Domain Idle Requirements
.................................................................................
37
1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions ................................ 39
1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions ................................ 41
1-26. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions ......................... 42
1-27. USB System Control Register (USBSCR) Field Descriptions
.......................................................
44
1-28. RTC Power Management Register (RTCPMGT) Field Descriptions
...............................................
46
1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions ........................................................ 47
1-30. On-Chip Memory Standby Modes ....................................................................................... 48
1-31. Power Configurations ..................................................................................................... 50
1-32. Interrupt Table
.............................................................................................................
53
1-33. IFR0 and IER0 Bit Descriptions
.........................................................................................
54
1-34. IFR1 and IER1 Bit Descriptions ......................................................................................... 55
1-35. Die ID Registers ........................................................................................................... 57
1-36. Die ID Register 0 (DIEIDR0) Field Descriptions ....................................................................... 58
1-37. Die ID Register 1 (DIEIDR1) Field Descriptions
.......................................................................
58
1-38. Die ID Register 2 (DIEIDR2) Field Descriptions
.......................................................................
58
1-39. Die ID Register 3 (DIEIDR3[15:0]) Field Descriptions ................................................................ 59
1-40. Die ID Register 4 (DIEIDR4) Field Descriptions ....................................................................... 59
1-41. Die ID Register 5 (DIEIDR5) Field Descriptions ....................................................................... 59
1-42. Die ID Register 6 (DIEIDR6) Field Descriptions
.......................................................................
60
1-43. Die ID Register 7 (DIEIDR7) Field Descriptions
.......................................................................
60
1-44. EBSR Register Bit Descriptions Field Descriptions ................................................................... 62
1-45. RTCPMGT Register Bit Descriptions Field Descriptions ............................................................. 64
1-46. LDOCNTL Register Bit Descriptions Field Descriptions .............................................................. 65
1-47. LDO Controls Matrix
......................................................................................................
65
6 List of Tables SPRUFX5A – October 2010 – Revised November 2010
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