Texas Instruments TMS3320C5515 - Manual (Page 19)

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1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM)
The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform one
access per cycle (one read or one write). ROM can be accessed by the internal program or data buses,
but not the DMA buses. The ROM address space can be mapped by software to the external memory or
to the internal ROM via the MPNMC bit in the ST3 status register.
The standard device includes a Bootloader program resident in the ROM and the bootloader code is
executed immediately after hardware reset. When the MPNMC bit field of the ST3 status register is set
through software, the on-chip ROM is disabled and not present in the memory map, and byte address
range FE 0000h - FF FFFFh is directed to external memory space (extends CS5 address reach). A
hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at hardware reset.
However, the software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the
program and data buses. Each SAROM block can perform one word read access per cycle.
Table 1-4. SAROM Blocks
Memory Block CPU Byte Address Range CPU Word Address Range
SAROM0 FE 0000h - FE 7FFFh 7F 0000h - 7F 3FFFh
SAROM1 FE 8000h - FE FFFFh 7F 4000h - 7F 7FFFh
SAROM2 FF 0000h - FF 7FFFh 7F 8000h - 7F BFFFh
SAROM3 FF 8000h - FF FFFFh 7F C000h - 7F FFFFh
1.2.1.4 External Memory
The external memory space of the device is located at the byte address range 05 0000h - FF FFFFh. The
external memory space is divided into five chip select spaces. The synchronous space is activated by one
chip select pin (EM_CS0) or by a pair of chip selects pins (EM_CS0 and EM_CS1). Each asynchronous
chip select space has a corresponding chip select pin (called EMIF_CS[2:5]) that is activated during an
access to the chip select space.
The external memory interface (EMIF) provides the means for the DSP to access external memories and
other devices including: NOR Flash, NAND Flash, SRAM, mSDRAM, and SDRAM (see section 1.5 for
limitations). Before accessing external memory, you must configure the EMIF through its registers. For
more detail on the EMIF, see the TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User’s
Guide (
SPRUGU6 ).
As described in Section 1.2.1.3 , when the MPNMC bit field of the ST3 status register is cleared (default),
the byte address range FE 0000h - FF FFFFh is reserved for the on-chip ROM, which decreases the
addressable size for EM_CS5.
The EMIF provides a configurable 16-bit (synchronous or asynchronous) or 8-bit (asynchronous only) data
bus, an address bus width of up to 21-bits, and five dedicated chip selects, along with memory control
signals. To maximize power savings, the I/O pins of the EMIF can be operated at lower voltage
independently of other I/O pins on the DSP. Further power savings may be achieved by setting the EMIF
I/O pins to have slow slew rate, as described in
Section 1.7.3.4 .
1.2.1.4.1 Asynchronous EMIF Interface
The EMIF provides a configurable 16- or 8-bit data bus with address bus width of up to 21-bits, and six
dedicated chip selects, along with memory control signals. The cycle timings of the asynchronous
interface are fully programmable, allowing for access to a wide range of devices including NAND flash,
NOR flash, and SRAM as well as other asynchronous devices such as a TI DSP HPI interface. In NAND
mode, the asynchronous interface supports 1-bit ECC for 8- and 16-bit NAND flash and 4-bit ECC for 8-bit
NAND flash.
1.2.1.5 Synchronous EMIF Interface
The EMIF provides a 16-bit data bus with one or two dedicated chip selects for mSDRAM. Non-mobile
SDRAM can be supported under certain circumstances. The C5515 always uses a mobile SDRAM
initialization command sequence, but it is able to support SDRAM memories that ignore the BA0 and BA1
19 SPRUFX5A – October 2010 – Revised November 2010 System Control
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