Texas Instruments TMS3320C5515 User Manual
Page 56
Interrupts
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1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]
The CPU has only one interrupt flag that is shared among the three timers. The CPU's interrupt flag is bit
4 (TINT) of the IFR0 & IER0 registers (see Figure 1-25). Since the interrupt flag is shared, software must
have a means of determining which timer instance caused the interrupt. Therefore, the timer interrupt
aggregation flag register (TIAFR) is a secondary flag register that serves this purpose.
The timer interrupt aggregation flag register (TIAFR) latches each timer (Timer 0, Timer 1, and Timer 2)
interrupt signal when the timer counter expires. Using this register, the programmer can determine which
timer generated the timer aggregated CPU interrupt signal (TINT). Each Timer flag in TIAFR needs to be
cleared by the CPU with a write of 1. Note that the IFR0[TINT] bit is automatically cleared when entering
the interrupt service routine (ISR). Therefore there is no need to manually clear it in the ISR. If two (or
more) timers happen to interrupt simultaneously, the TIAFR register will indicate the two (or more)
interrupt flags. In this case, the ISR can choose to service both timer interrupts or only one-at-a-time. If the
ISR services only one of them, then it should clear only one of the TIAFR flags and upon exiting the ISR,
the CPU will immediately be interrupted again to service the second timer flag. If the ISR services all of
them, then it should clear all of them in the TIAFR flags and upon exiting the ISR, the CPU won't be
interrupted again until a new timer interrupt comes in. For more information, see the
TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide (
1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers
The CPU has only one interrupt flag that is shared among all GPIO pin interrupt signals. The CPU's
interrupt flag is bit 5 (GPIO) of the IFR1 & IER1 registers (see Figure 1-26). Since the interrupt flag is
shared, software must have a means of determining which GPIO pin caused the interrupt. Therefore, the
GPIO interrupt aggregation flag registers (IOINTFLG1 and IOINTFLG2) are secondary flag registers that
serve this purpose.
If any of the GPIO pins are configured as inputs, they can be enabled to accept external signals as
interrupts using the GPIO Interrupt Enable Registers (IOINTEN1 and IOINTEN2). The GPIO Interrupt Flag
Registers (IOINTFLG1 and IOINTFLG2) can be used to determine which of the 32 GPIO pins triggered
the interrupt. Note that the IFR0[GPIO] bit is automatically cleared when entering the interrupt service
routine (ISR). Therefore, there is no need to manually clear it in the ISR. If two (or more) GPIO pins
happen to interrupt simultaneously, the IOINTFLG1/IOINTFLG2 register indicates the two (or more)
interrupt flags. In this case, the ISR can choose to service both/all GPIO interrupts or only one-at-a-time. If
the ISR services only one of them, then it should clear only one of the IOINTFLG1/IOINTFLG2 flags and
upon exiting the ISR, the CPU is immediately interrupted again to service the others. For more
information, see the TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output (GPIO)
User's Guide (
).
1.6.5 DMA Interrupt Enable and Aggregation Flag Registers
The CPU has only one interrupt flag that is shared among the 16 DMA interrupt sources. The CPU's
interrupt flag is bit 8 (DMA) of the IFR0 & IER0 registers (see Figure 1-25). Since the interrupt flag is
shared, software must have a means of determining which DMA instance caused the interrupt. Therefore,
the DMA interrupt aggregation flag registers (DMAIFR) are secondary flag registers that serve this
purpose.
Each of the four channels of a DMA controller has its own interrupt, which you can enable or disable a
channel interrupt though the DMAnCHm bits of the DMA Interrupt Enable Register (DMAIER) (see
). The interrupts from the four DMA controllers are combined into a single CPU interrupt.
You can determine which DMA channel generated the interrupt by reading the bits of the DMA interrupt
flag register (DMAIFR). For more information, see the TMS320VC5505/VC5504 DSP Direct Memory
Access (DMA) Controller User's Guide (
).
56
System Control
SPRUFX5A – October 2010 – Revised November 2010
Copyright © 2010, Texas Instruments Incorporated