Texas Instruments TMS320VC5402 - Manual (Page 57)

TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
57 POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b, CLKXP = 0 †
(see Figure 31)
MASTER SLAVE
UNIT
MIN MAX MIN MAX
UNIT
tsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low 9 – 12H ns
th(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 0 5 + 12H ns
tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high 10 ns
tc(BCKX) Cycle time, BCLKX 12H 32H ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b,
CLKXP = 0† (see Figure 31)
PARAMETER
MASTER
‡
SLAVE
UNIT PARAMETER
MIN MAX MIN MAX
UNIT
th(BCKXL-BFXL) Hold time, BFSX low after BCLKX low§ T – 3 T + 4 ns
td(BFXL-BCKXH) Delay time, BFSX low to BCLKX high¶ C – 5 C + 3 ns
td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid –2 6 6H + 5 10H + 15 ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
C – 2 C + 3 ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H+ 4 6H + 17 ns
td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H – 2 8H + 17 ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
BCLKX
BFSX
BDX
BDR
tsu(BDRV-BCLXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
th(BCKXL-BFXL)
td(BFXL-BDXV)
td(BFXL-BCKXH)
LSB MSB tsu(BFXL-BCKXH)
tc(BCKX)
Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0