beautypg.com

Texas Instruments TMS320VC5402 User Manual

Page 40

background image

TMS320VC5402

FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

40

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

PS, DS

R/W

MSTRB

D[15:0]

A[19:0]

CLKOUT

th(D)R

th(CLKL-A)R

td(CLKL-MSH)

td(CLKL-A)

td(CLKL-MSL)

tsu(D)R

ta(A)M

ta(MSTRBL)

th(A-D)R

th(D)MSTRBH

NOTE A: A[19:16] are always driven low during accesses to external data space.

Figure 13. Memory Read (MSTRB = 0)