Texas Instruments TMS320VC5402 User Manual
Page 26
TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
26
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DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the ’5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
Reserved
TINT1
BRINT1
BXINT1
01b
Reserved
TINT1
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
Reserved