Texas Instruments TMS320VC5402 - Manual (Page 42)

TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
42 POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing (continued)
PS, DS
R/W
MSTRB
D[15:0]
A[19:0]
CLKOUT
td(CLKH-RWH)
th(A)W
td(CLKL-MSH)
tsu(D)MSH
td(CLKL-D)W
tw(SL)MS
tsu(A)W
td(CLKL-MSL)
th(D)MSH
td(CLKL-A)
td(CLKH-RWL)
td(RWL-MSTRBL)
td(CLKH-A)
ten(D-RWL)
tdis(RWH-D)
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 14. Memory Write (MSTRB = 0)