See figure 16) – Texas Instruments TMS320VC5402 User Manual
Page 44
TMS320VC5402
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
44
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memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a
parallel I/O port write
(IOSTRB = 0) [H = 0.5 t
c(CO)
]
†
(see Figure 16)
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address valid
–2
3
ns
td(CLKH-ISTRBL)
Delay time, CLKOUT high to IOSTRB low
–2
3
ns
td(CLKH-D)IOW
Delay time, CLKOUT high to write data valid
H–5
H+8
ns
td(CLKH-ISTRBH)
Delay time, CLKOUT high to IOSTRB high
–2
3
ns
td(CLKL-RWL)
Delay time, CLKOUT low to R/W low
–1
3
ns
td(CLKL-RWH)
Delay time, CLKOUT low to R/W high
–1
3
ns
th(A)IOW
Hold time, address valid after CLKOUT low
0
3
ns
th(D)IOW
Hold time, write data after IOSTRB high
H–3
H+7
ns
tsu(D)IOSTRBH
Setup time, write data before IOSTRB high
H–7
H+1
ns
tsu(A)IOSTRBL
Setup time, address valid before IOSTRB low
H–2
H+2
ns
† Address and IS timings are included in timings referenced as address.
IS
R/W
IOSTRB
D[15:0]
A[19:0]
CLKOUT
td(CLKH-ISTRBH)
th(A)IOW
th(D)IOW
td(CLKH-D)IOW
td(CLKH-ISTRBL)
td(CLKL-A)
td(CLKL-RWL)
td(CLKL-RWH)
tsu(A)IOSTRBL
tsu(D)IOSTRBH
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 16. Parallel I/O Port Write (IOSTRB = 0)