Intel SE8500HW4 - Manual (Page 87)

Intel® Server Board Set SE8500HW4 System BIOS
Revision 1.0
Intel order number D22893-001
75
10.3.1.4 Microcode Update API
Recent Intel processors have the capability of correcting specific errata through the loading of
an Intel-supplied data block (i.e. microcode update). The BIOS is responsible for storing the
update in nonvolatile memory and loading it into each processor during POST. The BIOS will
allow a number of microcode updates to be stored in the Flash, limited by the amount of free
space available. The BIOS performs the recommended update signature verification prior to
storing the update in the Flash. The system BIOS supports the real mode INT 15, D042
interface for updating the microcode updates in the flash.
10.3.1.5 Intel® Hyper-Threading Technology
64-bit Intel® Xeon™ Processors MP support Intel® Hyper-Threading Technology. By default,
the BIOS will detect processors that support this feature and enable it during POST. The BIOS
Setup provides an option to selectively enable or disable this feature.
The BIOS will create additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure will only show the physical processors installed. It will not
describe the virtual processors.
Because some operating systems are not able to efficiently utilize the Intel® Hyper-Threading
Technology, the BIOS will not have entries in the MP tables to describe the virtual processors.
10.3.1.6 Intel ® SpeedStep ® Technology
64-bit Intel ® Xeon™ Processors MP support the Geyserville3 (GV3) feature of Intel ®
SpeedStep ® Technology. This feature changes the processor operating ratio and voltage similar
to the Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2
feature. The Intel
® Server Board Set SE8500HW4 supports the GV3 feature in conjunction with
TM2 feature.
10.3.1.7 Intel ® Extended Memory 64 Technology
The Intel ® Server Board Set SE8500HW4 BIOS supports Intel ® Extended Memory 64
Technology (EM64T) for executing both 32-bit and 64-bit applications simultaneously.
10.3.2 Memory
ECC memory must be initialized by the BIOS before it can be used. The BIOS executes a
hardware memory test before configuring memory during POST and during runtime when a
Memory Board is hot inserted to the system. The memory test can be enabled or disabled
based on a BIOS setup option. During POST the hardware memory test is executed in parallel
on all Memory Boards before video is available. Hardware memory testing tests every byte of
memory location and cannot be stopped once initiated. The hardware isolates an uncorrectable
error down to a DIMM pair and a correctable error to a DIMM.
When the memory initialization test encounters bad DIMM(s), it disables the bad DIMM(s) and
turns on the corresponding DIMM error LED indicator on the Memory Board. The BIOS also
reports the correctable or uncorrectable error on the bad DIMM(s) and that the bad DIMM and
its bank partner DIMM has disabled. If bad DIMM(s) from the memory test results in the BIOS