Marvel Group Integrated Controller 88F6281 - Manual (Page 13)

List of Figures
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 13
List of Figures
1 Pin and Signal Descriptions ........................................................................................................... 17
Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18
2 Unused Interface Strapping ............................................................................................................ 49
3 88F6281 Pin Map and Pin List ........................................................................................................ 50
4 Pin Multiplexing ............................................................................................................................... 51
5 Clocking............................................................................................................................................ 60
6 System Power Up/Down and Reset Settings ................................................................................ 63
Figure 2: Power-Up Sequence Example..........................................................................................................64
Figure 3: Serial ROM Data Structure ...............................................................................................................70
Figure 4: Serial ROM Read Example...............................................................................................................71
7 JTAG Interface ................................................................................................................................. 73
8 Electrical Specifications (Preliminary) .......................................................................................... 75
Figure 5: SDRAM DDR2 Interface Test Circuit ................................................................................................91
Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91
Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................92
Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................92
Figure 9: RGMII Test Circuit ............................................................................................................................94
Figure 10: RGMII AC Timing Diagram ...............................................................................................................94
Figure 11: GMII Test Circuit ...............................................................................................................................95
Figure 12: GMII Output AC Timing Diagram ......................................................................................................96
Figure 13: GMII Input AC Timing Diagram.........................................................................................................96
Figure 14: MII/MMII MAC Mode Test Circuit......................................................................................................97
Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97
Figure 16: MII/MMII MAC Mode Input AC Timing Diagram................................................................................98
Figure 17: MDIO Master Mode Test Circuit .......................................................................................................99
Figure 18: MDC Master Mode Test Circuit ......................................................................................................100
Figure 19: SMI Master Mode Output AC Timing Diagram ...............................................................................100
Figure 20: SMI Master Mode Input AC Timing Diagram ..................................................................................100
Figure 21: JTAG Interface Test Circuit ............................................................................................................101
Figure 22: JTAG Interface Output Delay AC Timing Diagram .........................................................................102
Figure 23: JTAG Interface Input AC Timing Diagram ......................................................................................102
Figure 24: TWSI Test Circuit............................................................................................................................104
Figure 25: TWSI Output Delay AC Timing Diagram.........................................................................................104
Figure 26: TWSI Input AC Timing Diagram .....................................................................................................104
Figure 27: S/PDIF Test Circuit .........................................................................................................................106