3 smi master mode ac timing diagrams, Figure 18, Mdc master mode test circuit – Marvel Group Integrated Controller 88F6281 User Manual
Page 100: Figure 19, Smi master mode output ac timing diagram, Figure 20, Smi master mode input ac timing diagram
88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E
Copyright © 2008 Marvell
Page 100
Document Classification: Proprietary Information
December 2, 2008, Preliminary
Figure 18: MDC Master Mode Test Circuit
8.6.6.3
SMI Master Mode AC Timing Diagrams
Figure 19: SMI Master Mode Output AC Timing Diagram
Figure 20: SMI Master Mode Input AC Timing Diagram
CL
Test Point
MDC
MDC
MDIO
VIH(min)
VIH(min)
VIL(max)
tOVA
tOVB
MDC
MDIO
VIH(min)
VIH(min)
VIL(max)
tSU
tHO