10 inter-ic sound interface (i2s) ac timing, 1 inter-ic sound (i2s) ac timing table, 2 inter-ic sound (i2s) test circuit – Marvel Group Integrated Controller 88F6281 User Manual
Page 107: Table 58, Inter-ic sound (i2s) ac timing table, Figure 28, Inter-ic sound (i2s) test circuit, 10 inter-ic sound interface (i, S) ac timing, 1 inter-ic sound (i
Electrical Specifications
AC Electrical Specifications
Copyright © 2008 Marvell
Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Page 107
8.6.10
Inter-IC Sound Interface (I
2
S) AC Timing
8.6.10.1
Inter-IC Sound (I
2
S) AC Timing Table
Table 58: Inter-IC Sound (I
2
S) AC Timing Table
8.6.10.2
Inter-IC Sound (I
2
S) Test Circuit
Figure 28: Inter-IC Sound (I
2
S) Test Circuit
Description
Sym bol
Min
Max
Units
Notes
I2SBCLK clock frequency
fCK
MHz
2
I2SBCLK clock high/low level pulse w idth
tCH/tCL
0.37
-
tCK
1
I2SDI input setup time relative to I2SBCLK rise time
tSU
0.10
-
tCK
-
I2SDI input hold time relative to I2SBCLK rise time
tHO
0.00
-
ns
-
I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time
tOD
0.10
0.70
tCK
1
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 15 pF.
2. See "Reference Clocks" table for more details.
See note 2
CL
Test Point