Avago Technologies ACPL-224-500E - Manual (Page 20)

AV02-4387EN 17 Avago Technologies
Description
The above circuit shows how a 0 to 5
V logic signal can be level shifted to a
-15 to 0 V signal. The circuit can safely
be used for level shifting up to ±800
V. The circuit uses an open collector
output logic gate, the 74LS405, to
drive the LED of the HCPL-4502/3
optocoupler. The HCPL-4502/3 also
has an open-collector output. The
designer chooses R
IN
to agree with
the equation shown in the schemat-
ic. This equation sets the value of the
optocoupler LED forward current.
The output of the HCPL-4502/3 re-
quires a pull-up resistor, R
L
. The cur-
rent-transfer ratio (CTR) of the opto-
coupler determines the maximum
amount of current the optocoupler
output can sink while maintaining
the output voltage (between pins 5
and 6) of 0.5 V or less.
Performance of Circuit
• Maximum optocoupler propa-
gation delay: 2 µs (refer to al-
ternative Avago parts for lower
propagation delays)
• Typical signaling rate: dc to 1 MBd
(refer to alternative Avago parts
for higher speeds)
• Typical optocoupler LED drive
current: 10 to 16 mA
• Maximum output supply voltage
(pins 8-5): 30 V
• Minimum CMR: 15 kV/µs slew
rate, 1500 V peak
Benefits
• Reduces transient immunity
problems
• Convenient way of replacing
pulse transformer for high-volt-
age level shifting
Alternative Avago Parts
1) HCPL-07XX, HCPL-2730/1, HCPL-
4701, 6N138/9, HCNW138/9 Low
Input Current Optocouplers
2) HCPL-55XX Hermetically Sealed
High Speed Optocoupler
3) HCPL-0710 SO-8 High Speed
CMOS Optocoupler
4) HCPL-250L/260L/270L, HC-
PL-050L/060L/070L 3.3V Opto-
couplers
Level Shifting/TTL Interface with Shunt LED Drive
Digital Logic Interface/Level Shifting Applications
I
F
7
5
6
8
2
3
4
1
NOTE: FOR BEST CMR PERFORMANCE, CONNECT PIN 7 TO PIN 8.
IN R
74LS05
IN
R = 5 - V F
HCPL-4502/3
+5 V
I
F
L
R
OL V
-15 V
I
O
(min) = I
F
• CTR (min)
R
L
(min) = 15 – V
OL
I
O
(min) + I
IL
I IL I O
V IN
V OUT