Verilink DCSU 2911 (880-502647-001) Product Manual - Manual (Page 57)

DCSU 2911 E1 Craft Interface
Verilink DCSU 2911 User Manual 4-11
When finished configuring the port diagnostics parameters, enter X
to return to the Main Menu.
Performance/
Status Menu
Use the Performance/Status Menu to monitor the functioning and
condition of the ports. The parameters in this screen count the
various problems that occur in a given period of time. Performance
information is logged in 15-minute intervals over a 24-hour period.
To access the Performance/Status Menu from the Main Menu,
enter P.
Tn Test Pattern: Use this option to indicate one of the following options:
None: This option indicates that no test pattern will be used.
3 in 24: The 3-in-24 ONEs test pattern consists of three pulses in every
24-bit sequence (10001000 10000000 00000000). This stress test is
useful for testing circuits under extremely low density conditions. This
is mostly useful for T1 AMI.
QRSS: The Quasi-Random Signal Sequence limits the signal to a
maximum of 15 zeros in a row. These signals contain a medley of 20-
bit words (except for more than 15 consecutive 0s). It repeats every
1,048,575 bits. Also, it contains high density and low density
sequences, and sequences that change from low density to high density
and vice versa.
2N20-1: This pattern tests circuits for equalization and timing. It is the
same as QRSS, but without the 15 zeros restriction.
1/8: This pattern tests the ability of a circuit to support a pattern having
the minimum ones density (each byte has the sequence—1000000). It
helps discover a timing recovery problem. This is mostly useful for T1
AMI.
2N1 5-1: This pattern tests circuits for equalization and timing using an
alternate pattern for jitter testing. The pattern repeats every 32,757
bits.
All 0s: This pattern is composed entirely of framed zeros (00000000). It
should only be used in conjunction with HDB3 framing.
55 Octet: This Daly 55 octet pattern tests circuits for line module and
timing recovery. By rapidly transitioning from a long sequence of low
density octets to high density octets, the circuit is stress tested.
All 1s: This pattern is composed entirely of framed ones (11111111). It
stresses circuits by maximizing power consumption.
1) NONE
2) 3/24
3) QRSS
4) 2N20-1
5) 1/8
6) 2N15-1
7) ALL 0’S
8) 55 OCTET
(Daly)
9) ALL 1’S
An Send LLB codes: 1) DEACTIVATE
2) ACTIVATE
Bn Send PLB codes: 1) DEACTIVATE
2) ACTIVATE
En Reset Test Counter: This option resets the test counter to 0. The
counter is automatically reset when changing patterns.
X Exit the E1 Port Diagnostics Menu
Command Description Options