Sundance SMT916 - Manual (Page 9)

Digital inputs, just like analog inputs have got parallel diodes used as ESD
protection, which will prevent any input voltage higher than 5 volts to reach the
front-end.
A Buffer is used on each line to pass the signal to the FPGA.
Minimum Input levels: 1V peak-to-peak.
Maximum Input Level: 3.3V peak to peak.
Maximum frequency: 200MHz.
3.3.2.3 Digital output
There is one Digital Output, External Sync Out. It is part of the group of 4
connectors (bottom left of the board).
A Buffer is used between the FPGA and the connector.
Output Level: 0-3.3Volts
3.3.2.4 VCC/Ground planes
The module is powered from the SLB power module. Each ADC is connected to an
independent power rail in order to be less likely subject to cross-talk and shared
noises.
Each ADC channel will have its own independent ground plane and independent
power supplies. Each ADC ground plane will join (star type layout) the ‘SLB’ ground
plane in one point using 0-Ohm resistors.
3.3.2.5 ADC common mode voltage
The ADC common mode voltage is divided by 2 in the chip. It is then fed into an
opamp in order to ‘align’ analogue input and ADC internal voltages.
Figure 2 - ADCs common mode voltage.