Sundance SMT916 - Manual (Page 6)

1 Introduction
The SMT916 is an SLB mezzanine board that incorporates twelve AD7626 ADC chips
from Analog Devices (Two groups of six ADCs, Group A for the first six channels
and Group B for the next six channels). Converters are 16-bit SAR (Successive
Approximation Register), with a maximum throughput of 10MSPS. Analog input
connectors on the board all MMCX.
This module can be mated with one Sundance’s SLB base modules such as the
SMT351T (Virtex5 FPGA, DDR2 memory), SMT372T (Virtex5 FPGA coupled with two
6-core TI DSPs, Ethernet) or SMT700 (Virtex5 FPGA, PXIe bus, USB, Ethernet, SATA).
Note that the Base module is required to be set to 2.5V IOs in order not to damage
the SMT916.
ADCs will be working as two groups of 6 converters, all in ‘self-clocked’ mode. Each
group will be working simultaneously. The FPGA on the SLB base module is
responsible for triggering ADC conversions. The distribution of the conversion
signal will be ensured by two CDCLVD2106 chips from Texas Instrument. It features
low pin to pin skew (below 50ps) and low additive jitter (below 100ps).
Samples are collected by the FPGA using a serial LVDS link. Bits are clocked out of
the ADCs at a speed of 250MHz. Individual state machines synchronised to the
conversion signal ensure this process. The FPGA generates a serial clock that is be
distributed among the converters (2 groups of 6) using an LVDS clock distribution
chip (CDCLVD2106).
The front-end is implemented around 2 amplifiers (Analog Devices) allowing DC
levels. The input impedance will be 50 Ohms (or more depending on option
purchased). An anti-aliasing filter follows the amplifiers before signal reach the
ADCs. Cut-off frequency is half of the maximum ADC sampling rate (5MHz). ADCs
are driven differentially.
When it comes to synchronisation among several modules, an external clock input
(slave mode) and an external clock output (master mode) connectors are present as
well as a SYNC input connector to synchronise state machines between boards. An
external trigger is also present on the board. All four lines are connected to an FPGA
IO and protected by clamping diodes (3.3V). MMCX connectors are used.