Sundance SMT916 - Manual (Page 8)

The above block diagram shows how converters are driven and linked to the SLB
connector.
The FPGA implements states machines to generate conversion pulses. They are then
distributed to both groups (Group A and Group B) of 6 ADCs. Further in the state
machine, eighteen 250MHz clock cycles are generated to get the 16-bit sample out
of the converter (serial LVDS line) – 2 extra bits being used to synchronise data and
the fpga internal clock. This process will be repeated in order to collect more
samples.
The 250-MHz clock is distributed among the converter using a TI distribution chip.
LVDS lines are used between the FPGA, the clock distribution chips and the
analogue converters in order to avoid any noise to be picked up.
3.2 Module Description
Clock distribution chips are all from Texas Instrument. Converters are from Analog
Devices.
All MMCX connectors are accessible from the top of the module.
3.3 Interface Description
3.3.1 Mechanical Interface
The SMT916 comes as an SLB mezzanine module. It is coupled with an SLB base
module. The mezzanine plugs into the base module via an SLB data connector and
an SLB power connector. Some Nylon screws ensure that modules don’t move and
guarantee best connection.
The SMT916 does not follow the SLB specifications in terms of dimensions. The
board area will identical to an standard SLB base module.
3.3.2 Electrical Interface
3.3.2.1 Analogue inputs
All twelve analog inputs will be 50-ohm (other values are available on order)
terminated and accept signals within the range 0-4Volts.
Analog inputs have got parallel diodes used as ESD protection, which will prevent
any input voltage higher than 5 volts to reach the front-end.
3.3.2.2 Digital Inputs
There are 3 digital inputs, External Clock Input, External Trigger Input and External
Sync Input. They are part of the group of 4 connectors (bottom left of the board).