Sundance SMT916 - Manual (Page 3)

Table of Contents
1 Introduction ................................................................................................................... 6
2 Related Documents ....................................................................................................... 7
2.1 Referenced Documents .............................................................................................. 7
2.2 Applicable Documents ............................................................................................... 7
3 Functional Description ................................................................................................ 7
3.1 Block Diagram.............................................................................................................. 7
3.2 Module Description .................................................................................................... 8
3.3 Interface Description .................................................................................................. 8
3.3.1 Mechanical Interface .............................................................................................. 8
3.3.2 Electrical Interface ................................................................................................. 8
3.3.2.1 Analogue inputs ............................................................................................ 8
3.3.2.2 Digital Inputs ................................................................................................. 8
3.3.2.3 Digital output ................................................................................................ 9
3.3.2.4 VCC/Ground planes ..................................................................................... 9
3.3.2.5 ADC common mode voltage ....................................................................... 9
3.3.2.6 Input dual opamp structure ..................................................................... 10
3.4 Firmware ..................................................................................................................... 10
3.4.1 FPGA Block Diagram. ........................................................................................... 10
3.4.2 Global Control Register – 0x4 ............................................................................ 11
3.4.3 Global Status Register – 0x4 .............................................................................. 13
3.4.4 Conversion rate register channels 0 to 5 – 0x10. .......................................... 14
3.4.5 Conversion rate register channels 6 to 11 – 0x11. ........................................ 15
3.4.6 Storage Control Register – 0x12 ........................................................................ 15
3.4.7 ADCs Output Format GroupA – 0x13 .............................................................. 17
3.4.8 ADCs Output Format GroupB – 0x14 ............................................................... 17
3.4.9 Led Register – 0x15 .............................................................................................. 17
3.4.10 Channel Selection for read back operation – 0x20. ....................................... 18
3.4.11 Channel 0 – IODelay – 0x30. .............................................................................. 18
3.4.12 Channel 1 – IODelay – 0x31. .............................................................................. 18
3.4.13 Channel 2 – IODelay – 0x32. .............................................................................. 19
3.4.14 Channel 3 – IODelay – 0x33. .............................................................................. 19
3.4.15 Channel 4 – IODelay – 0x34. .............................................................................. 19
3.4.16 Channel 5 – IODelay – 0x35. .............................................................................. 20
3.4.17 Channel 6 – IODelay – 0x36. .............................................................................. 20
3.4.18 Channel 7 – IODelay – 0x37. .............................................................................. 20
3.4.19 Channel 8 – IODelay – 0x38. .............................................................................. 20
3.4.20 Channel 9 – IODelay – 0x39. .............................................................................. 21
3.4.21 Channel 10 – IODelay – 0x3A. ............................................................................ 21
3.4.22 Channel 11 – IODelay – 0x3B. ............................................................................ 21
4 Verification Procedures ............................................................................................. 22
5 Power Consumption – Heat dissipation. ................................................................ 22
5.1 AD7626 ADC Chip. ................................................................................................... 22