Table 13 : pci interrupt status register – Sundance SMT310 v.1.6 User Manual
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SMT310 User Manual V1.6
occurred on INTC
13
INTB_TO_D INTD output from INTB input: when set (1) an interrupt has
occurred on INTB
12
INTA_TO_D INTD output from INTA input: when set (1) an interrupt has
occurred on INTA
11
INTD_TO_C INTC output from INTD input: when set (1) an interrupt has
occurred on INTD
10 -
Reserved
9
INTB_TO_C INTC output from INTB input: when set (1) an interrupt has
occurred on INTB
8
INTA_TO_C INTC output from INTA input: when set (1) an interrupt has
occurred on INTA
7
INTD_TO_B INTB output from INTD input: when set (1) an interrupt has
occurred on INTD
6
INTC_TO_B INTB output from INTC input: when set (1) an interrupt has
occurred on INTC
5 -
Reserved
4
INTA_TO_B INTB output from INTA input: when set (1) an interrupt has
occurred on INTA
3
INTD_TO_A INTA output from INTD input: when set (1) an interrupt has
occurred on INTD
2
INTC_TO_A INTA output from INTC input: when set (1) an interrupt has
occurred on INTC
1
INTB_TO_A INTA output from INTB input: when set (1) an interrupt has
occurred on INTB
0 -
Reserved
Table 13 : PCI Interrupt Status Register
14.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0)
Bits
Name
Description
7
MAILBOX
Global mailbox interrupt enable
6
PCI_RD
PCI read error interrupt enable
5
PCI_WR
PCI write error interrupt enable
4 PCI_INT
Global
PCI
interrupt to local interrupt enable
3
PCI_PERR
PCI parity error interrupt enable
2
I2O_QWR
I2O inbound post queue write interrupt enable