Sundance SMT310 v.1.6 - Manual (Page 23)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
10 JTAG Controller
The SMT310 has an on board Test Bus Controller (TBC). The TBC is controlled from
the PCI bus giving access to the on site TIM and/or any number of external TIMs.
The TBC is a SN74ACT8990 from Texas Instruments. Please refer to the Texas
Instruments data sheet for details of this controller. The TBC is accessed in I/O space
at the Base address + 0x80.
TIM Site
TBC
8990
PCI Bus
External
JTAG out
Connector
Internal
JTAG out
(XDS-510)
Out
In0
In1
Switch
Buffer
Figure 2 : TBC Data Routing
The Test Bus Controller drives the JTAG scan chain through the TIM site on the
SMT310. If the site is not populated with a TIM then the modules SENSE signal is
used to enable a tri-state buffer connecting the TDI and TDO on the site (JTAG Data
In and Data Out) allowing TBC test data to appear at the external and internal JTAG
out connectors on the board. This switching is automatic. The External JTAG out
Connector is intended to connect to JTAG slaves external to the system chassis. The
Internal JTAG out (XDS-510) Header is for use with JTAG slaves within the system
chassis. Important Note – These connectors may not be used simultaneously.