2 pci interrupt status register(offset 0x48, bar0), Pci interrupt status register(offset 0x48, bar0), Table 12 : pci interrupt configuration register – Sundance SMT310 v.1.6 User Manual
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SMT310 User Manual V1.6
5
INTB_TO_LB 1=INTB will request LICU interrupts when the input is
active
0=INTB will never request LICU interrupts
4
INTA_TO_B When set INTA will act as interrupt request for INTB
output
3
INTD_TO_A When set INTD will act as interrupt request for INTA
output
2
INTC_TO_A When set INTC will act as interrupt request for INTA
output
1
INTB_TO_A When set INTB will act as interrupt request for INTA
output
0
INTA_TO_LB 1=INTA will request LICU interrupts when the input is
active
0=INTA will never request LICU interrupts
Table 12 : PCI Interrupt Configuration Register
14.3.2 PCI Interrupt Status Register(Offset 0x48, BAR0)
Bits Name
Description
31 MAILBOX
Mailbox
Interrupt:
1=Mailbox interrupt request active
0=No mailbox interrupts pending
Cleared by clearing MAIL_RD_STAT and
MAIL_WR_STAT
30
LOCAL
Local bus direct interrupt:
1=Local bus master requests a PCI interrupt
0=No operation
This bit is set by writing 1 and cleared by writing 0
29-28 -
Reserved
27
OUT_POST I2O outbound post list not empty: (see V3 datasheet)
26 -
Reserved
25
DMA1
DMA channel 1 interrupt
24
DMA0
DMA channel 0 interrupt
23-15 -
Reserved
14
INTC_TO_D INTD output from INTC input: when set (1) an interrupt has