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SMT310 User Manual V1.6
Table of Contents
1
Introduction ..................................................................................................................................... 8
2
Functional Description .................................................................................................................... 9
3
Setting Up the SMT310................................................................................................................. 10
4
Memory Map ................................................................................................................................. 11
4.1
PCI Bridge Chip Internal Register (BAR0) ........................................................................... 11
4.2
I/O Space Register Assignments (BAR1) ............................................................................ 11
4.3
Memory Space Assignments(BAR2).................................................................................... 12
5
DSP Resource Memory Map ........................................................................................................ 13
6
Shared Memory Resource ............................................................................................................ 14
7
Sundance Digital Bus (SDB)......................................................................................................... 15
8
ComPorts ...................................................................................................................................... 16
8.1
Buffered ComPort................................................................................................................. 17
9
ComPort to PCI Interface.............................................................................................................. 19
9.1
ComPort Registers (Offset 0x10, BAR1).............................................................................. 19
9.2
Control Register (Offset 0x14, BAR1) .................................................................................. 19
9.3
Status Register (Offset 0x14, BAR1 , Read-Only) ............................................................... 20
9.4
Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 21
10
JTAG Controller ............................................................................................................................ 23
11
Using the SMT310 External/Internal JTAG with TI Tools. ............................................................ 24
12
Firmware Upgrades ...................................................................................................................... 25
13
Global/Local Bus Transfers, DSP <-> PCI................................................................................... 27
13.1
Mailbox Accesses................................................................................................................. 27
13.1.1
Doorbell Interrupts ....................................................................................................... 28
13.2
DSP Interrupt Control ........................................................................................................... 28
13.3
DSP To Local Aperture 0 control and Accessing................................................................. 29
13.3.1
Global bus access protocol ......................................................................................... 31
14
Interrupts ....................................................................................................................................... 34
14.1
SMT310-To-PCI Interrupts ................................................................................................... 34
14.2
PCI-To-SMT310 Interrupts ................................................................................................... 35
14.3
Interrupt Registers................................................................................................................ 35
14.3.1
PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 35
14.3.2
PCI Interrupt Status Register(Offset 0x48, BAR0) ...................................................... 37
14.3.3
Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 38
14.3.4
Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 39
14.3.5
PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0) ................................................................................................................................. 39
