Sundance PARS - Manual (Page 8)

Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email: [email protected] Tel: +1 (775) 827-3103 www.sundancedsp.com
8.2.1. Description ..........................................................................................................................................58
8.2.2. DSP Target ..........................................................................................................................................60
8.2.3. FPGA Target .......................................................................................................................................60
8.2.4. Profiling Output...................................................................................................................................60
8.3. L EAST M EAN SQUARE E RROR ...................................................................................................................60
8.3.1. Description ..........................................................................................................................................60
8.3.2. DSP Target ..........................................................................................................................................60
8.3.3. FPGA Target .......................................................................................................................................60
8.3.4. Profiling Output...................................................................................................................................60
8.4. A COUSTIC N OISE CANCELLATION ..............................................................................................................60
8.4.1. Description ..........................................................................................................................................60
8.4.2. DSP Target ..........................................................................................................................................60
8.4.3. FPGA Target (?)..................................................................................................................................60
8.4.4. Profile Output......................................................................................................................................60
8.5. F EEDBACK C ONTROL SYSTEM (GM) .........................................................................................................60
8.5.1. Description ..........................................................................................................................................61
8.5.2. DSP Target ..........................................................................................................................................61
8.5.3. FPGA Target .......................................................................................................................................61
8.5.4. Profiling Output...................................................................................................................................61
8.6. AE ROSPACE G UIDANCE ............................................................................................................................61
8.6.1. Description ..........................................................................................................................................61
8.6.2. DSP Target ..........................................................................................................................................61
8.6.3. Profiling Output...................................................................................................................................61
9. INSTALLATION .............................................................................................................................................62
9.1. R ESTRICTIONS ...........................................................................................................................................62
9.2. I NSTALLED H IERARCHY ............................................................................................................................62
9.3. S TEP - BY - STEP W ALKTHR U .......................................................................................................................62
9.4. V ERIFYING THE INSTALLATION ..................................................................................................................62
10. ADDONS......................................................................................................................................................63
10.1. O VERVIEW ................................................................................................................................................63
10.2. SMT6045 (U NIVERSAL T ARGET S ERVICES )..............................................................................................63
10.2.1. Overview .........................................................................................................................................63
10.2.2. Features ..........................................................................................................................................63
10.2.3. Installed Hierarchy .........................................................................................................................63
10.2.4. Pre-Built Task Descriptions............................................................................................................63
10.2.5. DSP Interface Descriptions ............................................................................................................63
10.2.6. HOST Interface Descriptions..........................................................................................................63
10.2.7. FPGA Modules Descriptions ..........................................................................................................63
10.3. M ODULES ..................................................................................................................................................63
10.3.1. Overview .........................................................................................................................................63
10.3.2. Features ..........................................................................................................................................63
10.3.3. Installed Hierarchy .........................................................................................................................63
10.3.4. Pre-Built Task Descriptions............................................................................................................63
10.3.5. DSP Interface Descriptions ............................................................................................................63
10.3.6. HOST Interface Descriptions..........................................................................................................63
10.3.7. FPGA Modules Descriptions ..........................................................................................................64
10.4. SCOM (S UNDANCE C OMMUNICATION I NTERFACE ) ..................................................................................64
10.4.1. Overview .........................................................................................................................................64
10.4.2. Features ..........................................................................................................................................64
10.4.3. Installed Hierarchy .........................................................................................................................64
10.4.4. Nomenclature..................................................................................................................................64