Sundance PARS - Manual (Page 47)

Revision 11-wip-7
Page 47 of 70
Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email: [email protected] Tel: +1 (775) 827-3103 www.sundancedsp.com
Task Placement Selection
Target Processor Selection
Task Memory Size Field
Task Parameters Field
4.2.3. GRT vs. ERT
Examples
4.3. FPGA TASKS
4.3.1. Overview
4.3.2. Mask Options
Task Placement Selection
Clock Source Field
4.3.3. Clock Domain Considerations
4.3.4. HDLCoder vs. Xilinx System Generator
Examples
4.4. PARS DIAMOND LIBRARY
4.4.1. Overview
4.4.2. Diamond Blockset
Diamond Configuration Block
DSPLink Block
memblock Block
Bind Input Block
Bind Output Block
Task Input Block
Task Output Block
4.4.3. Device Driver Tasks