Sundance PARS - Manual (Page 10)

Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email: [email protected] Tel: +1 (775) 827-3103 www.sundancedsp.com
Figure 25 - Generate application................................................................................................................................ 27
Figure 26 - PARS working......................................................................................................................................... 28
Figure 27 - PARS finished, testbench generated ....................................................................................................... 28
Figure 28 – Link-layer interface selection ................................................................................................................. 29
Figure 29 - AddOne model running on hardware ...................................................................................................... 29
Figure 30 - Select target with FPGA.......................................................................................................................... 30
Figure 31 - Select "HDL Coder" FPGA task creation mode...................................................................................... 30
Figure 32 - Re-assign DSP task to FPGA task........................................................................................................... 31
Figure 33 - AddOne model on FPGA task ................................................................................................................. 31
Figure 34 - Simulate, then generate the re-targeted application ................................................................................ 32
Figure 35 - PARS Generates FPGA-based application.............................................................................................. 32
Figure 36 - FPGA model execution on hardware (note the error) ............................................................................. 33
Figure 37 - FPGA Execution with pipeline delay (correct) ....................................................................................... 33
Figure 38 - PARS workflow and automation............................................................................................................. 34
Figure 39 - Simulink model Solver parameters.......................................................................................................... 36
Figure 40 - Simulink model Hardware Implementation parameters .......................................................................... 37
Figure 41 - Selecting a hardware profile.................................................................................................................... 38
Figure 42 - Processors and wires in a hardware system............................................................................................. 40
Figure 43 - How routing is implemented between processors ................................................................................... 41
Figure 44 - Setting data types on Input/Output ports ................................................................................................. 42
Figure 45 - Shortcut buttons on PARS control panel................................................................................................. 43
Figure 46 - General DSP task parameters panel ........................................................................................................ 43
Figure 47 - Filter Bank original model....................................................................................................................... 59
Figure 48 - PARS versions as seen by Matlab ........................................................................................................... 62
Table 1 - Matrix of PARS features vs. tools required................................................................................................ 14
Table 2 - Model Parameters for Code Generation ..................................................................................................... 37
Table 3 - Allowable connection data types in PARS................................................................................................. 42