Sundance PARS - Manual (Page 44)

Revision 11-wip-7
Page 44 of 70
Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email: [email protected] Tel: +1 (775) 827-3103 www.sundancedsp.com
The specific controls available on this panel are described in detail in sections 4.2.2. and
4.3.2. below, for DSP and FPGA subsystems respectively. On the panel, the ‘Place task
on’ parameter gives a drop-down list box with each of the processors listed of the
allocated type.
For example, suppose a hardware topology contains two DSP processors and one FPGA. Then, each
DSP task would have the name of the DSP processors in the list, but not the FPGA processors. The
same for the FPGA task parameter panel, which would have only one FPGA choice listed.
If your active hardware topology does not have any of a particular kind of processor, then the menu
option and the button are disabled.
3.6. PRE-BUILT TASKS
3.6.1. DSP PB Tasks
3.6.2. FPGA PB Tasks
3.6.3. SCOM PB Tasks
3.7. HOST TESTBENCH STRATEGY
3.8. GENERATING APPLICATIONS
3.8.1. Pre-Compiled Libraries
3.8.2. FPGA Processors in Designs
When targeting FPGA processors in designs, it is important to avoid naming the subsystem with
keywords that are used in the VHDL language. For example, one should not use a subsystem name
‘Generate’, as that will create conflict with the VHDL parser.