Sundance PARS User Manual
Page 5
Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email:
Tel: +1 (775) 827-3103
www.sundancedsp.com
TABLE OF CONTENTS
1.
PREFACE.........................................................................................................................................................11
1.1.
I
NTENDED
A
UDIENCE
................................................................................................................................11
1.2.
R
ELATED DOCUMENTATION
......................................................................................................................11
1.3.
TRADEMARKS ......................................................................................................................................11
2.
INTRODUCTION TO PARS..........................................................................................................................12
2.1.
OVERVIEW.............................................................................................................................................12
2.1.1.
What is PARS?.....................................................................................................................................12
2.1.2.
Features...............................................................................................................................................13
2.1.3.
Benefits ................................................................................................................................................13
2.2.
REQUIREMENTS ...................................................................................................................................13
2.3.
DEVELOPMENT
FLOW ........................................................................................................................14
2.4.
WALKTHRU
................................................................................................................................................16
3.
MODEL DEVELOPMENT ............................................................................................................................34
3.1.
O
VE
R
VIEW
................................................................................................................................................34
3.1.1.
How PARS works with a model ...........................................................................................................34
3.2.
P
REPARING FOR CODE GENERATION
..........................................................................................................35
3.2.1.
Solver Configuration ...........................................................................................................................36
3.2.2.
Hardware Implementation...................................................................................................................37
3.2.3.
Summary ..............................................................................................................................................37
3.3.
H
ARDWARE
P
ROFILE SELECTION
...............................................................................................................38
3.4.
P
ARTITIONING
...........................................................................................................................................39
3.4.1.
Connections between subsystems ........................................................................................................39
3.4.2.
Connections between processors .........................................................................................................39
3.4.3.
Data Types for Connections ................................................................................................................42
3.5.
A
LLOCATING PROCESSOR
R
ESOURCES
......................................................................................................43
3.6.
P
RE
-B
UILT
T
ASKS
.....................................................................................................................................44
3.6.1.
DSP PB Tasks......................................................................................................................................44
3.6.2.
FPGA PB Tasks ...................................................................................................................................44
3.6.3.
SCOM PB Tasks ..................................................................................................................................44
3.7.
H
OST TESTBENCH STRATEGY
....................................................................................................................44
3.8.
G
ENERATING APPLICATIONS
......................................................................................................................44
3.8.1.
Pre-Compiled Libraries.......................................................................................................................44
3.8.2.
FPGA Processors in Designs ..............................................................................................................44
3.9.
R
UNNING THE TEST BENCH
........................................................................................................................45
3.10.
R
ESTRICTIONS
...........................................................................................................................................45
3.11.
COMMON ISSUES
........................................................................................................................................45
3.11.1.
Loop Deadlock................................................................................................................................45
3.11.2.
Out-of-order Deadlock ...................................................................................................................45
3.11.3.
Rate Deadlock.................................................................................................................................45
4.
PARS COMPONENT REFERENCE ............................................................................................................46
4.1.
PARS
C
ONTROL
P
ANEL
..............................................................................................................................46
4.1.1.
Overview..............................................................................................................................................46
4.1.2.
File Menu ............................................................................................................................................46
4.1.3.
PARS Menu..........................................................................................................................................46
4.1.4.
Tool Menu............................................................................................................................................46
4.1.5.
Help Menu ...........................................................................................................................................46
4.2.
DSP
T
ASK
S...............................................................................................................................................46