Sundance PARS User Manual
Page 39
Revision 11-wip-7
Page 39 of 70
Sundance Digital Signal Processing, Inc.
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www.sundancedsp.com
3.4.
PARTITIONING
One of the caveats of working with PARS is that all blocks within a model be contained
in subsystems prior to code generation. Each subsystem will become an atomic unit of
execution in the embedded system.
It is important to assign all top-level objects to a subsystem. PARS does not interpret non-subsystems
in the PARS model, not even documentation objects. Typically, the documentation objects would be
placed in the ‘HOST’ subsystem, and would therefore translate to the testbench.
The goal of partitioning a model is to group tasks that might schedule independently of other
operations. For DSP applications, this means tasks which may execute on different processors, or
which may execute at different times/rates on the same processor. For FPGA applications this means
logic that can execute concurrently. The more subsystem partitions your model has, the greater
opportunity for parallelism and concurrency. The trade-off, of course, is that connections between
subsystems take a finite amount of time. This is typically not covered by simulation, unless it is
modelled by a transmission delay block.
Strictly speaking, a model is partitioned into subsystems irrespective of the underlying hardware. The
subsystems group logically related operations together. In PARS, grouping subsystems does require
some consideration of the underlying hardware communication mechanisms primarily to deal with
limited connection resources and dataflow I/O performance.
When a model is partitioned, subsystems connect to other subsystems through input and output ports.
These connections define the exchange of (numeric) data between the logic/operations implemented in
the (atomic) subsystem.
3.4.1.
Connections between subsystems
Connections between subsystems on the same processor are fast. On an FPGA they are implemented
by wires connecting the output and input stages together, often with a few cycles propagation delay.
On a DSP, they are implemented by operating-system defined libraries which currently involve a buffer
copy from the output buffer to the input buffer of the peer.
You can have an unlimited number of connections between subsystems on the same processor.
3.4.2.
Connections between processors
Connections between subsystems on different processors are subject to the type of link interface that
exists between them. A hardware system topology describes processors and the ‘wires’ linking them.
Each ‘wire’ declares a link interface between the two processors in a point-to-point manner. See Figure
42, below.
Hardware manufacturers provide details on pin-mappings, software drivers and/or firmware IP to
implement their link interfaces. As long as you can connect the processors using supported devices,
PARS can create applications of any complexity and any intermixture of hardware types.