Sundance PARS User Manual
Page 6
Sundance Digital Signal Processing, Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
email:
Tel: +1 (775) 827-3103
www.sundancedsp.com
4.2.1.
Overview..............................................................................................................................................46
4.2.2.
Mask Options.......................................................................................................................................46
4.2.3.
GRT vs. ERT ........................................................................................................................................47
4.3.
FPGA
TA
SKS
............................................................................................................................................47
4.3.1.
Overview..............................................................................................................................................47
4.3.2.
Mask Options.......................................................................................................................................47
4.3.3.
Clock Domain Considerations.............................................................................................................47
4.3.4.
HDLCoder vs. Xilinx System Generator..............................................................................................47
4.4.
PARS
D
IAMOND
LI
BRARY
........................................................................................................................47
4.4.1.
Overview..............................................................................................................................................47
4.4.2.
Diamond Blockset................................................................................................................................47
4.4.3.
Device Driver Tasks ............................................................................................................................47
4.4.4.
DSP Tasks............................................................................................................................................48
4.4.5.
FPGA Tasks.........................................................................................................................................48
4.4.6.
SCOM Tasks ........................................................................................................................................49
4.5.
DSP
P
RE
-B
UILT
TA
SKS
............................................................................................................................49
4.5.1.
Overview..............................................................................................................................................49
4.5.2.
Usage...................................................................................................................................................49
4.5.3.
Template of a DSP PB Task ................................................................................................................49
4.5.4.
CPBT Operation for DSP Tasks ..........................................................................................................49
4.5.5.
Bind Input Block ..................................................................................................................................49
4.5.6.
Bind Output Block ...............................................................................................................................49
4.5.7.
Examples .............................................................................................................................................50
4.6.
FPGA
P
RE
-BUILT
TASKS ......................................................................................................................50
4.6.1.
Overview..............................................................................................................................................50
4.6.2.
Usage...................................................................................................................................................50
4.6.3.
Template of an FPGA PB Task............................................................................................................50
4.6.4.
CPBT Operation for FPGA Tasks .......................................................................................................50
4.6.5.
Examples .............................................................................................................................................50
4.7.
SCOM
W
RAPPER
T
ASKS
...........................................................................................................................50
4.7.1.
Overview..............................................................................................................................................50
4.7.2.
Usage...................................................................................................................................................50
4.7.3.
Hierarchy of SCOM Task Wrappers....................................................................................................50
4.7.4.
SCOM Task Table................................................................................................................................50
4.7.5.
Deriving New Variants ........................................................................................................................50
4.7.6.
Examples .............................................................................................................................................50
4.8.
H
ARDWARE
D
ESCRIPTION
F
ILE
.................................................................................................................50
4.8.1.
Overview..............................................................................................................................................50
4.8.2.
Sections (.m file based input)...............................................................................................................50
4.8.3.
Model Based Input (.mdl file) ..............................................................................................................51
5.
PARS GENERATED CODE ..........................................................................................................................52
5.1.
PARS
H
IERARCHY
....................................................................................................................................52
5.2.
DSP
T
ASKS
...............................................................................................................................................52
5.2.1.
Structure ..............................................................................................................................................52
5.2.2.
Files (Production)................................................................................................................................52
5.2.3.
Variants ...............................................................................................................................................52
5.3.
FPGA
T
ASKS
............................................................................................................................................52
5.3.1.
Structure ..............................................................................................................................................52
5.3.2.
Common Files......................................................................................................................................52
5.3.3.
Scalar vs. Vector Inputs.......................................................................................................................52
5.3.4.
Files .....................................................................................................................................................52
5.4.
P
RE
-BUILT
T
ASKS
...................................................................................................................................53