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Sundance PARS User Manual

Page 33

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Revision 11-wip-7

Page 33 of 70

Sundance Digital Signal Processing, Inc.

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.

email:

[email protected]

Tel: +1 (775) 827-3103

www.sundancedsp.com

Now that the application has completed, we can execute it as before.

Figure 36 - FPGA model execution on hardware (note the error)

Notice that the FPGA-based implementation has a difference. This is due to a pipeline stage that exists
in the FPGA implementation. Effectively, the FPGA output is delayed by one simulation step.

Figure 37 - FPGA Execution with pipeline delay (correct)

Adding this delay in the testbench shows that the model is behaving in an appropriate manner.

In summary, this walkthrough has shown how to use PARS to take a Simulink model and execute it on
hardware in a very straightforward manner. It has also shown how easy it is to re-target designs from
DSP to FPGA and explore trade-offs in the implementation space.