Measurement Computing CIO-DAS16/330 - Manual (Page 24)

Counter section
Counter type 82C54
Configuration Two 82C54 devices, 3 down counters each device, 16 bits each
82C54A:
Counter 0 - Independent, available to user
Source: 100 kHz on board clock or external (CTR 0 Clock In)
Gate:
External (Dig In 2 / CTR 0 Gate)
Output: Available at user connector (CTR 0 Out)
Counter 1 - ADC Pacer Lower Divider
Source: 1 or 10 MHz oscillator, jumper-selectable
Gate:
Tied to Counter 2 gate, programmable source (internal or external
(Dig In 0 / Trigger).
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source: internal or external
(Dig In 0 / Trigger).
Output: ADC Pacer clock, available at user connector (CTR 2 Out)
82C54B:
Counter 0 - Total samples (residual) counter upper divider
Source: Counter 1 output (total samples lower divider)
Gate:
Internal
Output: Internal
Counter 1 - Total samples (residual) counter lower divider
Source: ADC conversion complete
Gate:
Tied to Counter 2 gate, internal source.
Output: Counter 0 input (total samples upper divider)
Counter 2 - Trigger index counter
Source: ADC conversion complete
Gate:
Tied to Counter 1 gate, internal source.
Output: Not used
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Crystal oscillator
Frequency 10 MHz
Frequency accuracy 100 ppm
Environmental
Operating temperature range 0 to 50°C
Storage temperature range − 20 to 70°C
Humidity 0 to 90% non-condensing
20