Measurement Computing CIO-DAS16/330 - Manual (Page 19)

BIT 6 - Pre-Trigger Enable. Trigger Status.
WRITE: 0 = Disable pre-trigger mode. 1 = enable pre-trigger. The trigger index counter (CTR 2 of 2nd 8254) is
gated to the packet interrupt. Because it is gated to the FIFO packet interrupt, the trigger flushes the FIFO at the
instant of the trigger, ensuring the only samples prior to and all samples prior to the trigger are in the pre-trigger
buffer.
READ: Valid only when pre-trigger is enabled. 0 = Trigger has not yet occurred. 1 = Trigger occurred.
BIT 7 - DT-CONNECT Enable/Disable & Status
WRITE: 0 = Disable DT-Connect. 1 = Enable DT-CONNECT.
For DT-Connect to operate, the Total Counter output must be forced low. The simplest way to do this is to write the
value 16 to Base +19 (both decimal).
READ: 0 = DT-CONNECT is disabled. 1 = DT-CONNECT is enabled.
4.11 PACER CLOCK DATA & CONTROL REGISTERS
8254 COUNTER 0 DATA
BASE ADDRESS + 12
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
8254 COUNTER 1 DATA
BASE ADDRESS + 13
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
8254 COUNTER 2 DATA
BASE ADDRESS + 14
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
The three 8254 counter/timer data registers may be written to and read from. Because each counter will count to 65,535,
loading or reading the counter data is a multi-step process. The operation of the 8254 is explained in the section on the
counter/time and the Intel 8254 data sheet.
8254 COUNTER CONTROL
BASE ADDRESS + 15
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
This register controls the operation and loading/reading of the counters. The configuration of the 8254 codes which
control the 8254 chip is explained in the section on the counter timer and the Intel 8254 data sheet.
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