Measurement Computing CIO-DAS16/330 - Manual (Page 14)

4.4 A/D DATA & CHANNEL REGISTERS
Note: When in enhanced mode, the bus interface is 16 bits wide and BASE +0 and BASE +1 should be read as a 16 bit
pair. To whit, the register at BASE + 1 should be read as the most significant eight bits of a 16-bit read to BASE + 0.
BASE ADDRESS
CH1 CH2 CH4 CH8 A/D12
LSB
A/D11 A/D10 A/D9
0 1 2 3 4 5 6 7
A read/write register.
READ
On read, it contains two types of data. The least significant four digits of the analog input data and the associated
channel number.
These four bits of analog input data must be combined with the eight bits of analog input data in BASE + 1, forming
a complete 12-bit number. The data is in the format 0 = minus full scale. 4095 = +FS.
The channel number is binary. The weights are shown in the table above. If the current channel were 5, then bits
CH4 and CH1 would be high, CH8 and CH2 would be low.
WRITE
Writing any data to the register causes an immediate A/D conversion.
BASE ADDRESS +1
A/D8 A/D7 A/D6 A/D5 A/D4 A/D3 A/D2 A/D1
MSB
0 1 2 3 4 5 6 7
A Read-only register.
On read, the most significant A/D byte is read.
4.5 CHANNEL MUX SCAN LIMITS REGISTER
BASE ADDRESS +2
CH L1 CH L2 CH L4 CH L8 CH H1 CH H2 CH H4 CH H8
0 1 2 3 4 5 6 7
A read and write register.
READ
The current channel scan limits are read as one byte. The high channel number scan limit is in the most significant
four bits. The low channel scan limit is in the least significant four bits.
WRITE
The channel scan limits desired are written as one byte. The high channel number scan limit is in the most significant
four bits. The low channel scan limit is in the least significant four bits.
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