Zilog EZ80190 - Manual (Page 81)

eZ80190 Development Kit
User Manual
General Array Logic Equations UM014108-0810
77
//Flash on the Module will be
//disabled if nDIS_FL is High
wire nEXP_EN = ~((nCS0==0)&(A7==0)&(A6==1));//
expansion module
//Flash enabled if this is 0
//wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);
wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them
is 0 Flash is
//disabled
assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN :
~(nEX_FL_DIS);
assign nL_RD =
~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0
)|(nEM_EN==0)|(nCS_EX==0));
assign nmemen4 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h17));
assign nmemen3 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h16));
assign nmemen2 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h15));
assign nmemen1 =
~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h14));
assign nEM_EN =
~((nCS2==0)&({A7,A6,A5,A4,A3,A2,A1,A0}==8'h80));
endmodule
U15 Address Decoder
`define anode 8'h00