Zilog EZ80190 - Manual (Page 55)

eZ80190 Development Kit
User Manual
UM014108-0810 Operational Description
51
eZ80190 Module Memory
The eZ80190 Module contains 512 KB SRAM and 1 MB Flash memory.
This addressing structure provides 1.5 MB of contiguous RAM for imme-
diate use.
SRAM Memory
The eZ80190 Module features 512 KB of fast SRAM. Access speed is
typically 12 ns or faster, allowing zero-wait-state operation at 50 MHz.
With the CPU at 50 MHz, onboard SRAM can be accessed with zero wait
states. CS1_CTL (chip select CS1) is set to
08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are
held permanently in Flash memory.
Internal RAM
The eZ80190 MCU features 8 KB of zero-wait-state internal SRAM. This
internal RAM can be mapped anywhere in the 16 MB address space in the
address range
E000h – FFFFh .
Reset Generator
The onboard Reset Generator Chip is connected to the eZ80190 Reset
input pin. It performs reliable Power-On Reset functions, generating a
reset pulse with a duration of 200 ms if the power supply drops below
2.93 V. This reset pulse ensures that the board always starts in a defined
condition. The RESET pin on the I/O connector reflects the status of the
RESET line. It is a bidirectional pin for resetting external peripheral com-
ponents or for resetting the eZ80190 Development Kit with a low-imped-
ance output (e.g. a 100-Ohm push button).