Search
beautypg.com
Directory
Brands
Altera manuals
Measuring instruments
Data Conversion HSMC
Manual
Altera Data Conversion HSMC User Manual
Data conversion hsmc reference manual
Text mode
Original mode
Altera Data Conversion HSMC User Manual | 44 pages
Pages:
1
2
3
4
5
6
7
…
44
wrong Brand
wrong Model
non readable
Table of contents
Document Outline
Contents
1. Overview
General Description
Components and Block Diagram
Components
Block Diagram
2. Board Components and Interfaces
Board Overview
Configuration, Status, and Setup Elements
A/D Converter Clock Select Jumper (J3, J7)
Power Down Select Jumper (J2, J6)
D/A Converter Clock Select Jumper (J15, J17)
Mode Select Jumper (J11)
Gain Select Jumper (J10)
Sleep Select Jumper (J13)
External Clock Output Select Jumper (J23)
Clocks
External Clock Input SMA Connectors (J26, J30)
External Clock Output SMA Connectors (J25, J28)
Component Interfaces
A/D Converter (U1, U2)
A/D Converter Input SMA Connector (J4, J8)
D/A Converter (U3)
D/A Converter Output SMA Connector (J12, J14)
Audio CODEC Converter (U5)
Audio Jacks (J19, J20, J21, J42)
HSMC Connector (J1)
I2C Serial EEPROM (U14)
Power Supply
A/D Power Supplies (U6, U7, U8)
Additional Information
Revision History
How to Contact Altera
Typographic Conventions
See also other documents in the category Altera Measuring instruments:
MAX 10 JTAG
(15 pages)
MAX 10 Power
(21 pages)
Unique Chip ID
(12 pages)
Remote Update IP Core
(43 pages)
Device-Specific Power Delivery Network
(28 pages)
Device-Specific Power Delivery Network
(32 pages)
Hybrid Memory Cube Controller
(69 pages)
ALTDQ_DQS IP
(117 pages)
MAX 10 Embedded Memory
(71 pages)
MAX 10 Embedded Multipliers
(37 pages)
MAX 10 Clocking and PLL
(86 pages)
MAX 10 FPGA
(26 pages)
MAX 10 FPGA
(56 pages)
USB-Blaster II
(22 pages)
GPIO
(22 pages)
LVDS SERDES
(27 pages)
User Flash Memory
(33 pages)
ALTDQ_DQS2
(100 pages)
Avalon Tri-State Conduit Components
(18 pages)
Cyclone V Avalon-MM
(166 pages)
Cyclone III FPGA Starter Kit
(36 pages)
Cyclone V Avalon-ST
(248 pages)
Stratix V Avalon-ST
(286 pages)
Stratix V Avalon-ST
(293 pages)
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP
(10 pages)
Arria 10 Avalon-ST
(275 pages)
Avalon Verification IP Suite
(224 pages)
Avalon Verification IP Suite
(178 pages)
FFT MegaCore Function
(50 pages)
DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP
(140 pages)
Floating-Point
(157 pages)
Integer Arithmetic IP
(157 pages)
Embedded Peripherals IP
(336 pages)
JESD204B IP
(158 pages)
Low Latency Ethernet 10G MAC
(109 pages)
LVDS SERDES Transmitter / Receiver
(72 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(3 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(80 pages)
IP Compiler for PCI Express
(372 pages)
Parallel Flash Loader IP
(57 pages)
Nios II C2H Compiler
(138 pages)
RAM-Based Shift Register
(26 pages)
RAM Initializer
(36 pages)
Phase-Locked Loop Reconfiguration IP Core
(51 pages)
DCFIFO
(28 pages)