I2c serial eeprom (u14), C serial eeprom (u14) – Altera Data Conversion HSMC User Manual
Page 22
2–16
Chapter 2: Board Components and Interfaces
Component Interfaces
Data Conversion HSMC Reference Manual
© November 2008
Altera Corporation
shows the HSMC connector layout.
I
2
C Serial EEPROM (U14)
There is a 2-Kbit I
2
C Serial EEPROM on the Data Conversion HSMC.
lists
the I
2
C Serial EEPROM board reference and manufacturing information.
provides the pin-out details of the I
2
C Serial EEPROM with HSMC
connector.
Figure 2–7. Samtec Header Connector
2.413
((90 POS / 30 x .7875) + .050)
.78 REF
.626 REF
.036 REF
.006 REF
.245 REF
.150 REF
01
02
.285 REF
DP Bank
.571
(29 EQ Spaces @ .0197)
Table 2–19. I
2
C Serial EEPROM Component Reference
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U14
2-Kbit I
2
C Serial EEPROM
ISSI
IS24C02B
Table 2–20. I
2
C Serial EEPROM (U14) Pin-Out Information
HSMC Signal
HSMC Pin
Device Signal
Device
Pin Number
Description
SCL
34
SCL
6
Serial Clock Input
SDA
33
SDA
5
Serial Address/Data I/O
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)