Altera Data Conversion HSMC - Manual (Page 30)

A–6 Appendix A: Pin-Out Information for the Cyclone III (3C120)
Development Board
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
71 LVDS TX 4p or CMOS I/O data bit 20 ADA_D3 HSMB_TX_D_P4 LVDS or
2.5 V
R27
72 LVDS RX 4p or CMOS I/O data bit 21 ADB_D3 HSMB_RX_D_P4 LVDS or
2.5 V
L27
73 LVDS TX 4n or CMOS I/O data bit 22 ADA_D2 HSMB_TX_D_N4 LVDS or
2.5 V
R28
74 LVDS RX 4n or CMOS I/O data bit 23 ADB_D2 HSMB_RX_D_N4 LVDS or
2.5 V
L28
77 LVDS TX 5p or CMOS I/O data bit 24 ADA_D1 HSMB_TX_D_P5 LVDS or
2.5 V
R25
78 LVDS RX 5p or CMOS I/O data bit 25 ADB_D1 HSMB_RX_D_P5 LVDS or
2.5 V
M27
79 LVDS TX 5n or CMOS I/O data bit 26 ADA_D0 HSMB_TX_D_N5 LVDS or
2.5 V
R26
80 LVDS RX 5n or CMOS I/O data bit 27 ADB_D0 HSMB_RX_D_N5 LVDS or
2.5 V
M28
83 LVDS TX 6p or CMOS I/O data bit 28 ADA_OR HSMB_TX_D_P6 LVDS or
2.5 V
U25
84 LVDS RX 6p or CMOS I/O data bit 29 ADB_OR HSMB_RX_D_P6 LVDS or
2.5 V
P25
85 LVDS TX 6n or CMOS I/O data bit 30 ADA_OE HSMB_TX_D_N6 LVDS or
2.5 V
U26
86 LVDS RX 6n or CMOS I/O data bit 31 ADB_OE HSMB_RX_D_N6 LVDS or
2.5 V
P26
89 LVDS TX 7p or CMOS I/O data bit 32 ADA_SPI_CS HSMB_TX_D_P7 LVDS or
2.5 V
V27
90 LVDS RX 7p or CMOS I/O data bit 33 ADB_SPI_CS HSMB_RX_D_P7 LVDS or
2.5 V
P27
91 LVDS TX 7n or CMOS I/O data bit 34 AD_SDIO HSMB_TX_D_N7 LVDS or
2.5 V
V28
92 LVDS RX 7n or CMOS I/O data bit 35 AD_SCLK HSMB_RX_D_N7 LVDS or
2.5 V
P28
95 LVDS or CMOS clock out FPGA_CLK_A_P HSMB_CLK_OUT_P1 LVDS or
2.5 V
AC26
96 LVDS or CMOS clock in XT_IN_P HSMB_CLK_IN_P1 LVDS or
2.5 V
J27
97 LVDS or CMOS clock out FPGA_CLK_A_N HSMB_CLK_OUT_N1 LVDS or
2.5 V
AD26
98 LVDS or CMOS clock in XT_IN_N HSMB_CLK_IN_N1 LVDS or
2.5 V
J28
Table A–2. HSMC Port B Interface Pin-Out Information (Part 2 of 4)
Data Conversion HSMC Schematic Development Board Schematic
Board
Reference
(J1) Description
Schematic
Signal Name
Schematic
Signal Name
I/O
Standard
Cyclone
III
Pin
Number