Altera Cyclone V GX FPGA Development Board User Manual
Page 58
3–2
Chapter 3: Board Components Reference
Cyclone V GX FPGA Development Board
May 2013
Altera Corporation
Reference Manual
U4
3-Gbps HD/SD SDI adaptive cable
equalizer
National
Semiconductor
LMH0384SQ
J14
2x7 debug header
Samtec
TSW-107-07
U6, U15,
U21, U22
16M×16×8, 128-MB DDR3 SDRAM
Micron
MT41J128M16
U19, U23
16M×8×8, 128-MB DDR3 SDRAM
Micron
MT41J128M8
U37
1024K×18 bit 18-MB synchronous
SRAM
Integrated Silicon
Solution, Inc.
IS61VPS102418A-
250TQL
U18
512-MB synchronous flash
Numonyx
PC28F512P30BF
U17
16-channel differential 24-bit ADC
Linear Technology
LTC2418CGN#PBF
Table 3–1. Component Reference and Manufacturing Information
Board
Reference
Component
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)