Altera Cyclone V GX FPGA Development Board - Manual (Page 42)

2–34 Chapter 2: Board Components
Memory
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Table 2–29 lists the DDR3A pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GX in terms of I/O setting and
direction.
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
DDR3 x16 (U21)
N3 DDR3A_A0 AJ12 1.5-V SSTL Class I Address bus
P7 DDR3A_A1 AK12 1.5-V SSTL Class I Address bus
P3 DDR3A_A2 AH11 1.5-V SSTL Class I Address bus
N2 DDR3A_A3 AH12 1.5-V SSTL Class I Address bus
P8 DDR3A_A4 AG13 1.5-V SSTL Class I Address bus
P2 DDR3A_A5 AG14 1.5-V SSTL Class I Address bus
R8 DDR3A_A6 AK10 1.5-V SSTL Class I Address bus
R2 DDR3A_A7 AK11 1.5-V SSTL Class I Address bus
T8 DDR3A_A8 AF11 1.5-V SSTL Class I Address bus
R3 DDR3A_A9 AG11 1.5-V SSTL Class I Address bus
L7 DDR3A_A10 AJ8 1.5-V SSTL Class I Address bus
R7 DDR3A_A11 AK8 1.5-V SSTL Class I Address bus
N7 DDR3A_A12 AJ7 1.5-V SSTL Class I Address bus
T3 DDR3A_A13 AK7 1.5-V SSTL Class I Address bus
M2 DDR3A_BA0 AH9 1.5-V SSTL Class I Bank address bus
N8 DDR3A_BA1 AH10 1.5-V SSTL Class I Bank address bus
M3 DDR3A_BA2 AJ10 1.5-V SSTL Class I Bank address bus
K3 DDR3A_CASN AF9 1.5-V SSTL Class I Row address select
K9 DDR3A_CKE AK18 1.5-V SSTL Class I Column address select
J7 DDR3A_CLK_P Y13
Differential 1.5-V SSTL
Class I
Differential output clock
K7 DDR3A_CLK_N AA14
Differential 1.5-V SSTL
Class I
Differential output clock
L2 DDR3A_CSN Y12 1.5-V SSTL Class I Chip select
E7 DDR3A_DM0 AE15 1.5-V SSTL Class I Write mask byte lane
D3 DDR3A_DM1 AH19 1.5-V SSTL Class I Write mask byte lane
E3 DDR3A_DQ0 AF15 1.5-V SSTL Class I Data bus byte lane 0
H8 DDR3A_DQ1 AE16 1.5-V SSTL Class I Data bus byte lane 0
F7 DDR3A_DQ2 AJ14 1.5-V SSTL Class I Data bus byte lane 0
H7 DDR3A_DQ3 AH15 1.5-V SSTL Class I Data bus byte lane 0
F2 DDR3A_DQ4 AE17 1.5-V SSTL Class I Data bus byte lane 0
G2 DDR3A_DQ5 AD17 1.5-V SSTL Class I Data bus byte lane 0
F8 DDR3A_DQ6 AJ15 1.5-V SSTL Class I Data bus byte lane 0
H3 DDR3A_DQ7 AF14 1.5-V SSTL Class I Data bus byte lane 0
A7 DDR3A_DQ8 AK17 1.5-V SSTL Class I Data bus byte lane 1