Usb-blaster port, Expansion headers – Altera Cyclone II FPGA Starter Development Board User Manual
Page 43

Altera Corporation
Reference Manual
2–25
October 2006
Cyclone II FPGA Starter Development Board
Development Board Components
USB-Blaster Port
The Cyclone II FPGA Starter Board includes USB-Blaster circuitry used
for programming the FPGA or the EPCS4 device. A USB type B connector
(
) provides the connection to this programming circuitry.
Refer to
“USB-Blaster Controller” on page 2–2
for more information about
the USB Blaster circuitry.
Figure 2–19. USB Type B Connector
Expansion Headers
The development board provides two, 40-pin expansion headers, JP2,
located on the right edge of the board, and JP1, located next to it
(
). Each header connects directly to 36 pins on the FPGA, and
also provides DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins.
Each pin on the expansion header connects to a resistor that provides
protection from high and low voltages. The 40-pin header accepts a
standard 40-pin ribbon cable used for IDE hard drives.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)