Altera Cyclone II FPGA Starter Development Board User Manual
Page 30

2–12
Reference Manual
Altera Corporation
Cyclone II FPGA Starter Development Board
October 2006
Development Board Components
Figure 2–6. Flash Memory Interface Connections Diagram
lists the FPGA pins assigned to the flash memory.
Table 2–8. Flash Memory FPGA Pin Connections (Part 1 of 2)
Signal Name
FPGA Pin
Description
FL_ADDR[0]
PIN_AB20
FLASH Address[0]
FL_ADDR[1]
PIN_AA14
FLASH Address[1]
FL_ADDR[2]
PIN_Y16
FLASH Address[2]
FL_ADDR[3]
PIN_R15
FLASH Address[3]
FL_ADDR[4]
PIN_T15
FLASH Address[4]
FL_ADDR[5]
PIN_U15
FLASH Address[5]
FL_ADDR[6]
PIN_V15
FLASH Address[6]
FL_ADDR[7]
PIN_W15
FLASH Address[7]
FL_ADDR[8]
PIN_R14
FLASH Address[8]
FL_ADDR[9]
PIN_Y13
FLASH Address[9]
FL_ADDR[10]
PIN_R12
FLASH Address[10]
FL_ADDR[11]
PIN_T12
FLASH Address[11]
FL_ADDR[12]
PIN_AB14
FLASH Address[12]
FL_ADDR[13]
PIN_AA13
FLASH Address[13]
FL_ADDR[14]
PIN_AB13
FLASH Address[14]
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)