Altera Cyclone II FPGA Starter Development Board - Manual (Page 27)

Altera Corporation Reference Manual 2–9
October 2006 Cyclone II FPGA Starter Development Board
Development Board Components
SRAM Schematic and Pin List
Figure 2–5 shows the SRAM interface signals.
DRAM_ADDR[7] PIN_P5 SDRAM Address[7]
DRAM_ADDR[8] PIN_P3 SDRAM Address[8]
DRAM_ADDR[9] PIN_N4 SDRAM Address[9]
DRAM_ADDR[10] PIN_W3 SDRAM Address[10]
DRAM_ADDR[11] PIN_N6 SDRAM Address[11]
DRAM_DQ[0] PIN_U1 SDRAM Data[0]
DRAM_DQ[1] PIN_U2 SDRAM Data[1]
DRAM_DQ[2] PIN_V1 SDRAM Data[2]
DRAM_DQ[3] PIN_V2 SDRAM Data[3]
DRAM_DQ[4] PIN_W1 SDRAM Data[4]
DRAM_DQ[5] PIN_W2 SDRAM Data[5]
DRAM_DQ[6] PIN_Y1 SDRAM Data[6]
DRAM_DQ[7] PIN_Y2 SDRAM Data[7]
DRAM_DQ[8] PIN_N1 SDRAM Data[8]
DRAM_DQ[9] PIN_N2 SDRAM Data[9]
DRAM_DQ[10] PIN_P1 SDRAM Data[10]
DRAM_DQ[11] PIN_P2 SDRAM Data[11]
DRAM_DQ[12] PIN_R1 SDRAM Data[12]
DRAM_DQ[13] PIN_R2 SDRAM Data[13]
DRAM_DQ[14] PIN_T1 SDRAM Data[14]
DRAM_DQ[15] PIN_T2 SDRAM Data[15]
DRAM_BA_0 PIN_U3 SDRAM Bank Address[0]
DRAM_BA_1 PIN_V4 SDRAM Bank Address[1]
DRAM_LDQM PIN_R7 SDRAM Low-byte Data Mask
DRAM_UDQM PIN_M5 SDRAM High-byte Data Mask
DRAM_RAS_N PIN_T5 SDRAM Row Address Strobe
DRAM_CAS_N PIN_T3 SDRAM Column Address Strobe
DRAM_CKE PIN_N3 SDRAM Clock Enable
DRAM_CLK PIN_U4 SDRAM Clock
DRAM_WE_N PIN_R8 SDRAM Write Enable
DRAM_CS_N PIN_T6 SDRAM Chip Select
Table 2–6. SDRAM FPGA Pin Connections (Part 2 of 2)
Signal Name FPGA Pin Description