Power on/off switch, Run/prog switch, Fpga – Altera Cyclone II FPGA Starter Development Board User Manual
Page 33

Altera Corporation
Reference Manual
2–15
October 2006
Cyclone II FPGA Starter Development Board
Development Board Components
Power ON/OFF Switch
The Cyclone II FPGA Starter board receives its power from either the USB
port directly or the included 7.5V power adapter. The Power On/Off
switch gates the power from both of these sources to the rest of the board.
RUN/PROG Switch
The RUN/PROG switch directs the JTAG signals from the USB-Blaster
circuit to the FPGA directly when in the RUN position (
the EPCS4 Serial EEPROM configuration device when in the PROG
position (
).
Figure 2–8. RUN/PROG Switch in RUN Position
Figure 2–9. RUN/PROG Switch in PROG Position
With the RUN/PROG switch in the RUN position, the FPGA configures
from the EPCS4 device on power up.
USB Blaster Circuit
MAX
3128
USB
FPGA
JTAG Config Port
EPCS Serial
Configuration
Device
RUN/PROG
RUN”
Auto Power on Config
USB Blaster Circuit
MAX
3128
USB
FPGA
JTAG Config Port
EPCS Serial
Configuration
Device
RUN/PROG
PROG”
Auto Power on Config
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)