Altera Temperature Sensor User Manual
Page 9
Signals
Direction
Width (Bit)
Description
clr
Input
1
The asynchronous clear signal. When you assert the
clr
signal, the IP core sets the
tsdcalo[7:0]
signal
to
11010101
(
0xD5
) and the
tsdcaldone
signal to
0
.
This is an active-high signal. By default, this port
connects to GND.
tsdcalo[7:0]
Output
8
8-bit output signal that contains the analog-to-
digital-conversion temperature value. The 8-bit
value maps to a unique temperature value. During
device power-up or when you assert the
clr
signal,
the IP core sets the
tsdcalo[7:0]
to
11010101
(
0xD5
).
tsdcaldone
Output
1
This signal indicates the completion of the tempera‐
ture sensing process. The IP core asserts this signal
when the process is complete. During device power-
up or when you assert the
clr
signal, the IP core sets
the
tsdcaldone
to
0
.
Table 6: The Mapping of tsdcalo [7..0] Value to Arria V, Arria V GZ, Stratix IV, and Stratix V Devices
Temperature
This table shows the value of
tsdcalo[7:0]
that corresponds to the device temperature range. The temperature
specification ranges from -70° C to 127° C.
Value of tsdcalo[7:0] in Hexadecimal
Temperature in Degree Celsius (°C)
FF
127
...
...
E4
100
...
...
D5
85
...
...
D0
80
...
...
B2
50
...
...
9E
30
...
...
8A
10
...
...
80
0
...
...
76
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UG-01074
2015.05.04
Altera Temperature Sensor Signals
9
Altera Temperature Sensor IP Core User Guide
Altera Corporation