Altera Temperature Sensor - Manual (Page 4)

Note: When you choose not to create the
clr
port , the Altera Temperature Sensor IP core connects the
clr
port to GND. In this case, you must reset the device to clear the output signals or start a
temperature sensing operation. Altera recommends that you generate the
clr
port if you are
planning to run the temperature sensing operation more than once.
If a derived PLL output clock is used to drive the Altera Temperature Sensor IP core, a minimum pulse
violation might occur. When using the Altera Temperature Sensor IP core, you must ensure the clock
applied must be less than or equal to 1 MHz. If you are using a higher frequency clock, the Altera
Temperature Sensor IP core allows you use the 40 or 80 clock divider to reduce the clock frequency to be
less than or equal to 1.0MHz.
Related Information
Altera Temperature Sensor Signals on page 8
Provides more information about the value of tsdcalo[7:0] that corresponds to the device temperature
range.
Generating the Altera Temperature Sensor IP
To generate the Altera Temperature Sensor IP core, follow these steps:
1. Open the alttemp_sense_ex1.zip file and extract alttemp_sense_ex1.qar.
2. In the Quartus II software, open the alttemp_sense_ex1.qar file and restore the archive file into your
working directory.
3. On the IP Catalog window, search and click Altera Temperature Sensor.
4. In the New IP Instance dialog box, type
tsd_s4
as your top-level file name.
5. In the Device family field, select Stratix IV.
6. Then, select your FPGA device family from the Device Family pull-down list. Click OK.
7. In the Parameter Editor, set the following parameter settings.
Table 2: Configuration Settings for the Altera Temperature Sensor IP Core
Option Value
What is the input frequency? 40 MHz
What is the clock divider value? 80 MHz
Create a clock enable port Turned on
Create an asynchronous clear port Turned on
8. Click Finish. The
tsd_s4
module is built.
Compiling the Altera Temperature Sensor IP
To compile the Altera Temperature Sensor IP core in the Quartus II software, follow these steps:
1. Open the top-level file alttemp_sense_ex1.bdf in the Quartus II Block Editor software. This file
contains the input and output assignments and a placeholder for the
tsd_s4
module.
2. To insert the
tsd_s4
module, double-click on the Block Editor window. The Symbol window appears.
3. Under Name, browse to the tsd_s4.bsf file.
4. Click OK.
5. Place the
tsd_s4
module onto the INSERT TSD_S4 BLOCK HERE placeholder so that the module
aligns with the input and output ports.
4 Generating the Altera Temperature Sensor IP
UG-01074
2015.05.04
Altera Corporation Altera Temperature Sensor IP Core User Guide
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